The present invention relates generally to asynchronous semiconductor devices, and more specifically the invention pertains to an address transition detection circuit. Asynchronous devices require internal clock generator circuits in most cases. One prevalent method of generating the internal clock signals is Address Transition Detection (ATD), which is especially prominent in Static Random Access Memories (SRAMs). An ATD circuit creates an output pulse, or clock signal, when the input signal changes logic state. The clock signal is then used to time the internal operation. This operation differs from a synchronous device since the clock signal is generated by internal circuitry rather then provided by external circuitry.
The task of providing an ADT device to generate an internal clocking pulse for asynchronous devices is alleviated, to some extent, by the systems disclosed in the following U.S. Patents, the disclosures of which are incorporated herein by reference:
U.S. Pat. No. 5,448,529 issued to Reddy;
U.S. Pat. No. 5,428,580 issued to Kawashima;
U.S. Pat. No. 5,343,082 issued to Han;
U.S. Pat. No. 5,306,958 issued to Reddy;
U.S. Pat. No. 5,267,216 issued to Gabillard; and
U.S. Pat. No. 5,159,574 issued to Kim.
The above-cited patents use ATD clock generators that can be improved by the present invention.